The ability to form an array of input/output (I/O) terminals across the surface of a semiconductor die, such as an integrated circuit (IC), at low cost and with little technological investment is very desirable to both IC manufacturers and end users. Some ICs are interconnected to the next level system through the use of tiny gold or aluminum wires. Wire bonded devices are currently the most prevalent, and wire bonding is the least expensive manner of interconnecting the IC to the outside world. However, an increasing number of ICs utilize metal bumps as I/O interconnects instead of wire bonds because metal bumps eliminate the electrical parasitics associated with wire bond loops. Die with bump I/O interconnects may also reduce the system level footprint of the IC. Most commonly, metal bumps are made of a lead-tin solder. The solder bumps are melted in contact with the system level interconnect to form a physical and electrical connection. Less commonly, the metal bumps are made of gold, nickel, or some combination of metals, such as lead-tin solder over a copper base, or gold-plated nickel bumps.
Metal bumps can be formed by a variety of processes, including evaporation of lead and tin, electroplating of gold, electroplating of copper and lead-tin solder, thermosonic gold wire ball bumping, and lead-tin solder wire bumping. Evaporation of lead and tin is one of the more prevalent bumping processes, but has several drawbacks. For example, the use of lead in the solder bumps is a potential environmental hazard due to lead toxicity, and expensive waste remediation is involved in the processing. Also, lead-tin solder bumps require from 183.degree.-370.degree. C. for the joining operation to the next level of interconnect. This temperature range imposes limits upon the materials of construction of the substrate to which the IC can be joined.
Gold and solder bumps can also be formed from wire stock, using extensions of standard wire bonding technology. The chief difference in using wires for bumping, as opposed to standard wire bonding, is that after a ball bond (the first bond in a conventional wire bonding process) is formed, a wire loop to a stitch bond (the second bond in a conventional wire bonding process) is not formed. Instead, the wire is broken off just above the initial ball bond, leaving a metal ball on the bond pad. If gold wire is used, it may be desirable to subsequently flatten the metal ball, which often includes a small protruding wire tail. If solder wire is used in a bump process, a heating operation may be used to melt the bumps, eliminating the tiny wire tail which melts and spheroidizes with the base ball. Like evaporative techniques, bumping processes involving wire bonding have disadvantages. One disadvantage is that the pitch of ball bumps formed from wire is limited to the ball bumping process pitch limitations of about 150 .mu.m. Another limitation of ball bumping may be imposed by the need to use compressive force, ultrasonic energy, and heat which may be needed to form the gold or solder bump. Ball bumping may limit the location of the bumps to sites which are not located above active circuitry of the IC due to the stresses imposed upon the structure during the bonding process. Also, wire ball bumping is undesirable in that it is generally better to ball bump individual die instead of entire wafers. This is due oxidation of bond pads in wafer regions which are bonded last, and the formation of excessive bump-to-bond pad reaction phase or phases on wafer regions which are bumped first. Oxidation or excess bond reaction phase can degrade bump adhesion. Throughput of ball bumping is also a disadvantage as compared to processes wherein the entire wafer can be processed in one process module.
Of all the currently available bumping technologies, only electroplating is capable of forming bumps with bump centerline spacings of less than, or equal to, 100 .mu.m. The evaporative techniques discussed above historically have been used to form bumps at a 250 .mu.m pitch. Recent developmental work using evaporation has reported pitches at 200 .mu.m and 150 .mu.m, which is generally accepted as the practical limit of evaporative processes. Electroplating processes for bump formation do not use the mechanical masking characteristic of the evaporative process. Instead, photoresist materials need to be applied to the wafer surface, and openings are formed in the resist in locations where bumps are to be plated. A disadvantage associated with electroplating processes to form bumps is that thin film deposition of bond pad barrier metals (typically titanium, tungsten, platinum, palladium, or chromium), must occur prior to the electroplating operation. In some instances, an electroless nickel/gold process may be used to form the bumps. In this instance, the thin film deposition may be avoided, but another operation involving the use of a highly alkaline zincate solution must be used to allow the subsequent electroless nickel plating process to perform properly, and for the deposited nickel to adhere well to the aluminum-based bond pad. These extra processing steps add cost, both in terms of material costs and decreased throughput.
Attempts to produce conductive thermoset epoxy bumps have also been reported. The bumps are formed by screen, or stencil, printing of the conductive epoxy onto the metal bond pads, followed by a partial curing of the epoxy bumps. Subsequent heating of the these bumped die, with bumps in contact with the conductors on the next level of interconnect, causes softening of the epoxy and adhesion to the contact pads to form the electrical connection. The formation of thermoset epoxy I/O bumps via a conventional screen printing process is limited by the relatively coarse ability of this process to control bump dimensions. The location, height, diameter, and cross-sectional shape of conductive epoxy bumps are difficult to control with screen or stencil printing processes.
Despite the variety of means available for forming conductive bumps for IC interconnection, a need exists for an improved process. Particularly desirable would be a process which is inexpensive, which is simple enough to be done by either the semiconductor manufacturer or end user of an IC, which does not involve elaborate thin film processing, which can be done at the wafer level for adequate throughput, which will allow low temperature processing, and which can achieve fine pitch spacings demanded in future generation devices.